The latest DSP equipment can handle very large signal routing matrices and mixing, plus a myriad of features, functions and control options. Organizing all this into an intuitive interface is a challenge, to say the least. ASPEN processors and the GUI present this complexity in a simple manner that maximizes the DSP power, eliminates the need to compile and download saved files to the hardware, and provides ALL available signal processing on all inputs, crosspoints and outputs at all times. Connections to the hardware operate in real time, so changes and settings take place immediately while the system is running.
Available Signal Processing
Optimized Architecture uses the full power of the available DSP resources to provide features and functions without wasting DSP power on mundane tasks like managing a constructed signal flow that may or may not be optimal.
The architecture and DSP firmware are characterized by the following features:
Rich signal processing tools in all models:
- Clipping detectors
- RMS level meters
- Active channel detector for every mix
- Input gain stages
- Noise reduction filter (NRF) on every input
- Automatic feedback elimination filters (ADFE) with eight notch filters
- Four stages of fourth-order input tone control filters
- 0-100 ms input delay, input compressors
- 48 automatic mixers with Lectrosonics’ patented automatic mixing algorithm that supports five mixing modes independently controllable for every crosspoint
- Eight stages of fourth-order equalizers on each output
- 0-250 ms output delay
- Output compressors
- Output limiters
- Output gain stages
- Output RMS level meters
- Four signal generators: white noise, pink noise, adjustable frequency sine wave and a sweep generator with programmable sweeping options
Additional signal processing the conference models:
- DTMF signal generator
- Line acoustic echo canceler
- Acoustic Echo Canceller (US Patent Pending)
Every signal processing block is available without restrictions. All of them on every input and every output channel can be activated simultaneously and set to any value without running out of DSP resources. There is no DSP resource meter (aka “gas gauge”) because it is not necessary.
Every DSP block can be enabled/disabled during normal operation and every parameter can be adjusted in real time using either the GUI based ASPEN controller or the command terminal interface via RS-232, USB, and ethernet ports. Every filter stage can implement any available filter type and their parameters can be adjusted across the entire frequency range.
All gain stages, i.e. input, output and crosspoint gains are implemented smoothly using crossfading in the logarithmic (dB) domain to prevent abrupt, and thereby audible, level changes.
The entire DSP signal chain is implemented in a single audio sample. At the 48 kHz sampling rate, this equates to 20.833 μs. The A-D converter at the input and the D-A converter at the output have much more latency, several audio frames in length.
The order of the signal processing blocks has been carefully determined according to best practices. For instance, the compressor and limiter are located at the end of the signal processing chain which results in adjusting the signal level after all other signal processing has been applied. The pre-determined order of signal processing tasks is not a restriction of flexibility and is not a weakness. It is, in fact, a strength and key benefit of the architecture because it guarantees optimal operation.
The units are stackable, which provides a practically unlimited number of input channels and 48 system wide available mixes. The DSP capacity scales proportionally with the number of inputs and outputs with minimal latency. Every additional unit adds only 6 audio samples (125 μs) of delay to the single unit’s 1.33 μs base delay (measured from analog input to analog output). 200 inputs are handled with only 4.33 ms latency (1.33 ms for the master PCB plus 24 additional PCBs at .125 ms each).
Inputs and outputs in separate units are automatically time aligned for up to 100 units in a stack.
The DSP firmware is written in assembly language and optimized for speed and audio performance. It takes full advantage of the SHARC® processors’ special features:
- SIMD architecture - Single Instruction Multiple Data in which the DSP uses two processing elements executing the same instruction on different data
- Chained DMA transfers (Direct Memory Access)
- Delay line DMA
- Register content switching
Whenever possible, the firmware processes two channels simultaneously to take full advantage of the SIMD architecture.
The entire DSP program and most of the data (except for some large arrays) and signal processing parameters are held in the on-chip memory to maximize speed. Intermediate variables are always held in registers which have extended precision (40-bit floating point resolution). This practice helps to keep the digital rounding errors below the audible level. The 40-bit extended precision uses 32 bits of mantissa which is equivalent to 192 dB dynamic range that is further extended by the exponent.
ASPEN processors also use one of the best digital filter implementation techniques: the resonator based digital filter architecture, with orthogonal state variables that guarantees minimal sensitivity for coefficient rounding as well as minimal rounding noise .
Analog Devices SHARC® DSPs
The ASPEN family audio processors were designed using the latest and most powerful SHARC® DSPs available from Analog Devices that were available at the time of product release.
ASPEN Bus Signal Flow
Each processor takes mix bus signals from the unit below it, adds signals from its inputs and passes the updated sub-mix to the next unit above it. These sub-mixes continue to accrue in the Forward Propagation and arrive at the Master unit at the top of the stack. The Master unit adds signals from its own inputs and generates the Final Mixes that are then propagated back to all units below it in the stack. The source for all outputs in all units in the stack are taken from the 48 Final Mixes.
Every unit in the stack has access to all 48 Final Mixes even if the unit itself has only a few physical outputs. This signal flow structure simplifies the setup of the signal routing and matrix assignments and also allows the use of any physical output on any unit in the stack to deliver any of the final mixes to an external device.
One of the advantages of this signal flow structure is realized when multiple physical outputs all deliver the same final mix signal to different locations. Each output can process the audio differently with unique settings for delay, filters, compressor, level and limiter to suit the needs of each location. For example, a particular final mix can be sent to an auditorium sound system from one output, to a small sound system in a lobby from a second output, and to a media feed outlet for recording from a third output, with each output having its own unique signal processing.
The variety of models in this series are created by combining “building block” circuit board assemblies:
- 8 input, 12 output mixer board
- 16 channel input only board
- 8 channel input only board
- Conference interface board (standard and wideband versions)
A single board can be enclosed by itself in a stand-alone 1RU chassis, or combined with another board in a 2RU chassis to create a variety of models. The 2RU models include an LCD with comprehensive access to all system settings and activity.
The Feature Bundle
The result of Optimized Architecture provides a full suite of signal processing features and functions in even the smallest ASPEN model - the SPN812. This is a single rack space 8 in/12 out processor that can address the entire ASPEN matrix.
Dual board models use two boards of one type or another to create a variety of models to suit the needs of a particular installation. Each additional board adds its own processing blocks. For example, the SPN1624 uses two 812 boards, so the number of processing blocks is twice the list at right, except for the matrix crosspoints (the matrix supports a maximum of 48 outputs).
Additional inputs are added to the matrix when additional processors are added to the stack with no practical limit.
The SPN812 includes the following:
ASPEN Signal Flow Diagram